1. Field of the Invention
The present invention relates to an image processor, and more particularly, it relates to an image processor comprising a plurality of processors processing input image data in parallel and outputting the processed image data.
2. Description of the Related Art
FIGS. 23A and 23B are block diagrams showing the structure of an image processor provided on a conventional digital copying machine. Referring to FIG. 23A, the image processor is formed by a CCD 901, an A-D conversion part 903, a shading correction and LOG conversion part 905, a variable power part 907, an MTF correction part 909, a γ correction part 911 and a binarization processing part 913.
The A-D conversion part 903 converts image data subjected to optical/electrical conversion by the CCD 901 to digital data. Thereafter the image data is sequentially subjected to image processing and then output to a printer or the like. The blocks 905 to 913 for the image processing perform synchronous pipeline processing to operate with the same clock.
FIG. 23B is a block diagram showing the structure of an image processor performing image processing with an MPU 917. This image processor employs the MPU 917 in place of the image processing blocks 905 to 913 shown in FIG. 23A. Such a device is capable of rewriting an image processing program at any time and hence has a high degree of freedom, although the same is inferior to the device employing synchronous pipeline processing in consideration of the operating speed. The processing time for each pixel varies with the load of processing due to asynchronous processing with the MPU 917. Therefore, this device requires an input memory 915 and an output memory 919 for the MPU 917, for the purpose of synchronization with an input unit and an output unit.
Japanese Patent Laying-Open No. 3-177961 (1991) discloses a multiprocessor control unit, which processes image data for one frame in block units with a plurality of MPUs of a parallel structure.
FIG. 24 is a block diagram showing the structure of such a multiprocessor control unit. The multiprocessor control unit is formed by a data flow control part 952, a feedback frame memory 951, a status register 953, MPU1 to MPU4, a feedback bus, an output image bus and an input image bus.
The data flow control part 952 monitors values of the status register 953 storing processing states of the MPU1 to MPU4 and busy conditions of the buses. The data flow control part 952 instructs each MPU to operate. In other words, the data flow control part 952 allocates a new block of image data to an MPU terminating processing. A free MPU sequentially processes image data sequentially input in a serial manner, so that the image data are output at random regardless of the input sequence.
When requiring a result of processing of a preceding frame, each MPU captures feedback data of a required area from the feedback frame memory 951 through the feedback bus.
In the device shown in FIG. 24 processing and outputting subsequent input data from the MPU terminating processing through the data flow control part 952, the MPU has no idling standby time. In this device outputting image data regardless of the sequence of input data, however, the output data must be rearranged.
In order to eliminate the necessity for such rearrangement of the output data, the data output timings of the MPUs may be adjusted. Such a method is now described.
FIG. 25 shows a state of image data of one frame divided into 4 by 6 (=24) blocks. In this case, the MPU1 to MPU4 process the blocks of columns L1 to L4 respectively. Referring to FIG. 26, data of blocks D00, D01, D02 and D03 are input in the multiprocessor control unit at a time T1, so that the MPU1 to MPU4 process the data of the blocks D00 to D03 respectively. At a time t2 when the MPU (MPU3 in FIG. 26) having the lowest processing speed terminates the processing, processed data Q00 to Q03 are sequentially output. At the same time, data of new blocks D11 to D13 are input at the time t2 and processed by the MPU1 to MPU4 respectively.
Thus, the data can be output along the sequence of the blocks due to such processing, to require no rearrangement.
In the method shown in FIG. 26, however, the MPUs have idling standby times although no rearrangement of the output data is necessary. Thus, the image processing cannot be performed at a high speed.